IBM Packs 100 Billion Transistors on a Fingernail. Its Last Breakthrough, From 2021, Still Isn't in Mass Production.

Four breakthroughs. Zero factories. On June 25, IBM Research unveiled the world's first sub-1 nanometer chip technology at the VLSI 2026 symposium, demonstrating a 0.7-nanometer transistor node (7 angstroms) built on a new architecture called nanostack. Roughly 100 billion transistors fit on a chip the size of a fingernail, nearly double the density of IBM's 2nm demonstration from May 2021. IBM Research Director Jay Gambetta told Barron's it represents "a completely new paradigm" and projected production "in as early as the next 5 years."

He is probably right about the paradigm, but he is almost certainly wrong about the timeline, and IBM's own history proves it.

Four Nodes, One Pattern

IBM has demonstrated the world's first chip at every major semiconductor node since 2015, and it has shipped exactly none of them: not one commercial processor, not one customer wafer, not one revenue dollar from manufacturing. In 2014, IBM sold its chip fabrication business to GlobalFoundries for $1.5 billion, paid GlobalFoundries an additional $1.5 billion to take it, and became a pure research licensor. Since then, IBM's semiconductor division has operated as the industry's most expensive crystal ball: reliably predicting where chipmaking is headed, years before anyone else can actually make it work at volume. Here is the record.

Node	IBM Lab Demo	First Commercial Production	Gap	Who Actually Shipped
7nm	July 2015	TSMC, Q2 2018 (Apple A12)	~3 years	TSMC, Samsung
5nm	June 2017	TSMC, Q2 2020 (Apple A14)	~3 years	TSMC, Samsung
2nm	May 2021	TSMC N2, Q4 2025	4.5 years	TSMC, Samsung; Rapidus targeting H2 2027
0.7nm	June 2026	IBM projects ~2031	~5 years (projected)	No partner named

Notice what is happening to the gap. At 7nm and 5nm, IBM demonstrated the technology roughly three years before foundries shipped commercial silicon. Both TSMC and Samsung were already pursuing those nodes independently; IBM's research validated the path and contributed specific techniques, particularly nanosheet transistor architecture, which IBM invented in 2017 and which now underpins gate-all-around designs at every major foundry. At 2nm, the gap widened to at least 4.5 years: IBM showed the chip in May 2021, Mukesh Khare predicted volume production "by 2024," and TSMC did not begin N2 volume shipments until Q4 2025. Japan's Rapidus, IBM's closest manufacturing partner, is still running pilot wafers and targeting mass production in the second half of 2027, six years after the original demo.

At 0.7nm, IBM projects five years, which, if the pattern holds, is optimistic.

What Nanostack Actually Does

Set aside the timeline question for a moment, because the technology itself is genuinely significant. Conventional chip scaling works by shrinking transistors laterally, fitting more side by side on the same plane. At atomic dimensions, that approach runs into quantum tunneling, leakage currents, and fabrication tolerances measured in single atoms. Nanostack takes a different route: stacking transistors vertically in two layers, with the second layer staggered rather than sitting directly above the first. IBM calls this "3D sequential integration," and the VLSI 2026 paper reports a functional CMOS inverter with the expected switching performance built this way.

Each layer can use different channel materials optimized independently for power or performance, held together by ultra-thin dielectric bonding that enables the fabrication of each tier as a distinct process step. IBM validated the design with three separate experimental demonstrations, confirming that the architecture is physically buildable and computes correctly.

None of this means it can be manufactured at scale, because building each upper layer must happen below 400°C to avoid damaging the connections underneath, a thermal budget constraint that MIT Technology Review noted introduces "significant" challenges. Any defect in either tier kills the entire chip, yields drop substantially when you add layers, and IBM has not disclosed yield data for the nanostack process.

SRAM Scaling and the AI Chip Math

Buried in a second VLSI 2026 presentation was a detail more immediately relevant than the headline transistor count: nanostack delivers 40 percent SRAM scaling. That number deserves its own calculation, because SRAM is the silent bottleneck strangling AI chip design.

Modern AI accelerators dedicate enormous die area to SRAM, the fast on-chip memory that keeps data close to processing cores. Nvidia's H100, built on TSMC's 5nm process, occupies approximately 814 mm² of silicon, and industry estimates place on-chip SRAM at 30 to 40 percent of that die area: roughly 244 to 326 mm² consumed by caches, register files, and shared memory that would otherwise be available for additional compute logic. SRAM bitcell scaling has lagged logic scaling for three consecutive node generations, a divergence that means transistors keep shrinking while the memory cells surrounding them barely budge.

A 40 percent reduction in SRAM area on a chip like the H100 would recover approximately 98 to 130 mm² of die space. At the transistor densities IBM claims for 0.7nm, that recovered area could accommodate 65 to 130 billion additional transistors of compute logic. This is likely why IBM projects that AI accelerators built on a 7-angstrom design could deliver roughly 7,000 trillion operations per second, compared to approximately 1,500 TOPS on current hardware. Nearly a 5x improvement, with much of the gain coming not from faster transistors but from space recovered by denser memory.

To be clear: these are projections for hardware that does not exist in commercial form, and IBM itself describes them as estimates for an unbuilt product. But the underlying math is sound, because if you free 30 percent more die area by shrinking SRAM and fill it with compute, you get roughly the performance multiplier IBM is claiming.

Cost Per Transistor Is Still Falling

Wafer prices are rising sharply at each new node: TSMC charges approximately $16,000 to $17,000 for a 5nm wafer, that climbs to roughly $20,000 at 3nm, and at 2nm, industry reports indicate pricing around $30,000 per wafer, a 50 percent jump from 3nm. Apple alone has secured nearly half of TSMC's initial 2nm capacity, and demand from AI customers has pushed tapeout volumes higher than any prior node in its first two years.

Rising wafer prices sound like a crisis for Moore's Law, but they are not, because what matters is cost per transistor, and that metric keeps improving as transistor density grows faster than price.

Node	Approx. Wafer Price	Transistor Density	Approx. Cost per Billion Transistors (per die)
TSMC N5 (5nm)	$16,000-17,000	~134M / mm²	~$10-11
TSMC N3 (3nm)	~$20,000	~260M / mm²	~$5-6
TSMC N2 (2nm)	~$30,000	~400M / mm² (est.)	~$4 (est.)
IBM 0.7nm (lab)	Unknown	~670M-1B / mm²	< $3 (projected)

Each node roughly halves the cost of a billion transistors while raising the price of a raw wafer by 30 to 50 percent. If 0.7nm follows this trajectory, cost per transistor could drop below $2 per billion, even at wafer prices that might exceed $40,000, which means chips would cost more to make but less per unit of computation. This is the real Moore's Law, the economic one, and it has held for decades even as the physics version buckles under the weight of atomic-scale manufacturing constraints that would have seemed insurmountable a generation ago.

Where Everyone Else Stands

IBM announced its 0.7nm demo into a competitive landscape moving fast from the production side.

TSMC started N2 volume production in Q4 2025 and is ramping toward 100,000 wafers per month through 2026, with its enhanced N2P variant and A16 node (featuring backside power delivery) both scheduled for volume production in the second half of this year. Beyond that, TSMC is developing its 1.4nm A14 node for post-2027 production, and its own complementary FET research addresses the same vertical-stacking concept IBM demonstrated. At 3nm, TSMC capacity is targeted at 190,000 wafers per month by Q4 2026, rising to 230,000 by 2027. Samsung and Intel are producing roughly 20,000 to 25,000 wafers per month at comparable nodes.

Intel announced on June 16 that its 18A-P process, an enhanced 1.8nm node, entered risk production, using RibbonFET gate-all-around transistors and PowerVia backside power delivery to achieve 9 percent more performance at the same power draw. Intel's Fab 52 is already running 18A wafers in volume for Panther Lake processors, making it one of the few foundries with both a production-ready advanced node and actual silicon coming off the line.

IBM's 0.7nm is at least two full generations ahead of anything shipping, which makes it a research milestone with genuine architectural innovation and zero near-term commercial relevance. Whether it matters depends entirely on whether Rapidus, Samsung, or another partner can turn the nanostack concept into silicon at acceptable yields within a timeframe that doesn't see TSMC and Intel arrive at similar density through their own R&D roadmaps. Rapidus has received total R&D assistance of 2.354 trillion yen (roughly $15 billion) from the Japanese government and 32 private-sector backers, but it hasn't shipped its first commercial wafer at 2nm yet, let alone committed to the 0.7nm process that IBM just demonstrated.

Limitations

Several caveats apply to this analysis, and they are significant enough to affect the conclusions drawn from the data. IBM does not disclose precise transistor density per square millimeter; "fingernail-sized" could mean 100 to 150 mm², creating a density range rather than a point estimate. SRAM area breakdowns for specific AI chips are approximations because Nvidia, AMD, and other designers do not publish exact die-area allocation data. Wafer pricing for a hypothetical 0.7nm node does not exist; the cost-per-transistor projection assumes the historical trend of 30 to 50 percent wafer price increases per full node continues. IBM has not disclosed manufacturing yield data for nanostack, and the 400°C thermal budget for upper layers is a significant constraint that could reduce effective yields below commercially viable thresholds. IBM's 7,000 TOPS projection is its own estimate for hardware that has not been built. Finally, TSMC and Intel are pursuing their own CFET and vertical stacking research independently, so IBM's architectural lead may narrow before any partner brings nanostack to production.

Strongest Counterargument

Dismiss IBM's track record at your peril. Every major foundry shipping chips today uses nanosheet architecture that IBM invented and demonstrated first, Samsung licenses IBM semiconductor IP directly, and TSMC's gate-all-around process descends from the same nanosheet concept IBM published in 2017. Rapidus exists as a company specifically because IBM's 2nm research gave Japan a plausible path back into leading-edge manufacturing. Qing Cao at the University of Illinois called IBM's nanostack alignment on full wafers "transformative." MIT Technology Review estimates the architecture could provide 10 to 15 years of continued scaling for data center workloads. IBM may never manufacture a chip, but the companies that do build their roadmaps on IBM's research. A five-year gap between demonstration and production is not a failure of relevance. It is the normal speed of the hardest manufacturing process humans have ever attempted.

What You Can Do

If you are investing in semiconductor stocks, understand the distinction between a research demonstration and a product announcement, because IBM shares jumped 6 percent in premarket trading on June 25 and gave back most of those gains within hours when the market weighed the five-year production timeline against the technical achievement. Buy the company that can manufacture at scale, not the one that demonstrates in the lab. If you are evaluating AI infrastructure purchases for a data center, plan around TSMC N2 and Intel 18A, the nodes shipping now or within 12 months, and do not build a procurement strategy around 0.7nm hardware that won't exist for half a decade. If you work in chip design, the SRAM scaling result is the finding most likely to affect your work in the near term: 40 percent SRAM area reduction changes the design space for cache-heavy AI accelerators at every node, not just 0.7nm, so read the VLSI 2026 paper directly. If you simply want to know whether Moore's Law is dead, the answer remains no, because cost per transistor is still falling, chips are getting more expensive to make and cheaper to use, and IBM just showed the road extends at least another decade. How fast anyone drives down that road is a manufacturing question, not a physics one.

The Bottom Line

IBM builds the future of semiconductor technology in Albany, New York, and then waits for someone else to manufacture it, a pattern it has repeated four times since 2015 with increasing accuracy and increasing delays. The 0.7nm nanostack is the most architecturally ambitious demonstration yet, introducing genuine 3D transistor stacking that could deliver close to 5x performance improvements for AI workloads while continuing the half-century decline in cost per transistor. None of that will matter commercially for at least five years, probably longer, based on how long the last breakthrough took to cross from laboratory to factory floor. In the semiconductor industry, being first to demonstrate and first to ship are two entirely different achievements, and IBM has owned one of them for a decade while conspicuously lacking the other.

Sources

IBM Newsroom (June 25, 2026). IBM Unveils World's First Sub-1 Nanometer Chip Technology. Communications Today
Xu, Y., Zhu, B., et al. (2026). NanoStack Transistor Architecture for CMOS 7A Node and Beyond. VLSI Technology and Circuits 2026. IBM Research
Reuters (June 25, 2026). IBM unveils tech for chip smaller than 1 nanometer in AI computing push. Reuters
Barron's (June 25, 2026). IBM Knows How to Make the World's Tiniest AI Chip. This Is Big. Barron's
Investor's Business Daily (June 25, 2026). IBM Touts World's First Sub-1 Nanometer Chip Technology. IBD
TrendForce (2025). TSMC 2nm Node Set for 60K Monthly Output, Prices 50% Above 3nm. TrendForce
The Register (February 2026). Rapidus lands $1.7B to chase 2nm chip production by 2027. The Register
Semiconductor Digest (May 2021). IBM Unveils World's First 2 nm Chip Technology. Semiconductor Digest
MIT Technology Review (June 25, 2026). IBM's Nanostack Chip Technology Extends Moore's Law Roadmap. Via Memeburn
Reuters (April 2026). Japan approves additional $4B for chipmaker Rapidus.