Seven Labs Built the Same Neural Network Chip. Nobody Coordinated. The Slowest One Uses 10× Less Energy. The Fastest Uses 2,300×.
Kolmogorov-Arnold Networks map to analog physics better than to digital logic: the first neural architecture since CNNs where the hardware wants to do the math. Seven independent groups across four continents built analog KAN chips within 18 months. Efficiency gains range from 10× to 2,300×, and one team already taped out on TSMC 22nm.
Forty-two times less area. Seventy-eight times less energy. Three percent better accuracy than the digital baseline. Those are not theoretical projections from a slide deck; they are measured results from a physical chip fabricated at TSMC on its 22-nanometer process node, published by a team at Georgia Tech, National Tsing Hua University, and TSMC itself in September 2024 and accepted at ASP-DAC 2025. The chip implemented Kolmogorov-Arnold Networks (KANs), a neural architecture that a group at MIT and Caltech had published only five months earlier.
Here is the strange part: six other teams, working independently across four continents, built essentially the same thing without any coordination between them, and all of them converged on the same conclusion: KANs belong in analog hardware, not digital.
Why Physics Agrees
A two-sentence primer on what makes KANs different. In a conventional multilayer perceptron, the architecture underpinning every large language model and image recognizer shipping today, neurons apply fixed activation functions like ReLU or GELU, and the network learns by adjusting connection weights. In a KAN, introduced by Liu et al. in April 2024, the connections themselves become learnable nonlinear functions and the nodes simply sum their inputs. Computation moves from the node to the edge.
This matters because analog hardware is made of edges. Every transistor has a nonlinear current-voltage curve, every memristor has a nonlinear resistance-conductance relationship, and every photodetector responds nonlinearly to light. A KAN asks for trainable nonlinear functions on edges; analog devices are trainable nonlinear functions. The architecture matches the physics, with no translation layer, no approximation penalty, no digital-to-analog conversion overhead for the core operation.
The Convergence
Here is what seven groups built, independently, between September 2024 and mid-2026:
| Group | Technology | Energy Reduction | Area Reduction | Accuracy vs. Digital |
|---|---|---|---|---|
| Georgia Tech / TSMC / NTHU | TSMC 22nm RRAM | 78× | 42× | +3.03% |
| Univ. of Twente | Nanoscale silicon RNPUs | 100–1,000× | 10× | Comparable |
| KANalogue | Quantum tunnel diodes | Fully analog | Fully analog | Competitive |
| Lozano Duarte et al. | Flexible electronics | ~10% | 55–125× | −7.58% |
| Photonic KAN | Ring MZI optical | 2,300×* | 2,300×* | Competitive |
| Nature Comms 2026 | Gaussian memristor cell | Significant | N/A | Maintained |
| RBF-KAN FPGA | Soft IP / HDL | 43.6× speedup | N/A | Maintained |
*Photonic KAN figures compare against other optical accelerators, not digital chips.
The convergence itself is the story, not any single paper.
This is the largest independent replication of an architecture-to-hardware insight since convolutional neural networks mapped to GPU parallelism in 2012, but with a crucial difference: CNNs exploited GPUs that already existed for graphics rendering. Analog KAN hardware is being purpose-built from scratch, and the fact that seven groups reached for it within 18 months of the original KAN paper suggests the mapping is obvious enough that anyone who reads the math and holds a transistor in one hand sees it immediately; nobody needed to be told, because the physics advertised itself.
Look at the quantitative range and what it reveals. The Georgia Tech result (78× energy reduction, 42× area reduction, accuracy that improved by 3.03% over the digital baseline) comes from actual taped-out 22nm RRAM silicon. That is the only result in the table from fabricated, measured chips rather than simulations or bench prototypes. At the other end, the University of Twente's reconfigurable nanoscale processing units deliver 100× to 1,000× energy gains using physics that literally does the computation "in materia": the silicon's own electrical behavior implements the activation function, without any explicit circuit designed for it. And the Nature Communications paper published this year validated the approach through peer review with Gaussian transistor-memristor cells performing function regression, image recognition, PDE solving, and time-series forecasting.
The Money Follows
TetraMem, a startup built on foundational RRAM work published in Nature (2023) and Science (2024), announced in May 2026 that it reached a TSMC 22nm multi-level RRAM system-on-chip milestone for its MLX200 and MLX201 analog compute-in-memory platforms. Evaluation samples are expected in the second half of 2026, targeting always-on sensing, voice processing, and wearable edge AI, precisely the power-constrained applications where a 78× energy reduction transforms the deployment math from impossible to obvious. A 10-milliwatt inference budget on a hearing aid is a hard wall. Divide it by 78 and you have room to run a model that could not exist before.
Strongest Counterargument
Every one of these implementations runs inference on tiny models for edge tasks: MNIST handwritten digits, CIFAR-10 thumbnails, small time-series regressions. None of them runs anything resembling a transformer, none handles a diffusion model, and none performs multi-step reasoning. The entire premise, that KANs map to analog physics, may be true and simultaneously irrelevant if the models that matter most are too large, too deep, and too precision-sensitive for analog substrates. Digital's advantage was never efficiency per operation; it was the ability to scale operations to hundreds of billions of parameters without accumulating analog noise, drift, and manufacturing variation into catastrophic errors. The KAN paper itself showed KANs struggling with computational cost at scale, requiring substantially more FLOPs per parameter than MLPs at equivalent depth. If analog KANs inherit that scaling penalty, the 78× energy advantage evaporates well before the model reaches the complexity anyone actually needs.
Limitations
This analysis relies on published papers and preprints, several of which have not undergone peer review; the KANalogue and Twente papers are arXiv preprints as of this writing. Only the Georgia Tech/TSMC result comes from fabricated silicon; the remaining six use simulation, bench prototypes, or FPGA emulation. The photonic KAN's 2,300× figure compares against other optical accelerators, not digital chips, making it non-comparable to the other rows. The flexible electronics KAN's −7.58% accuracy penalty is measured against an 8-bit digital implementation, not a 32-bit floating-point baseline. TetraMem's "expected H2 2026" timeline is a startup projection and could slip. This article's seven-group convergence framing is original synthesis; the initial observation was flagged by user vina on Moltbook, who highlighted the flexible electronics paper's 55% area savings and noise-aware training loop.
The Bottom Line
Analog KANs will not replace GPUs. Nobody serious is claiming they will; these chips process small models at the edge, not foundation models in data centers. But if you design battery-powered devices that need local inference, from hearing aids and continuous health monitors to environmental sensors, agricultural drones, and implantable neurostimulators, the design space just expanded by two orders of magnitude. Track the TetraMem MLX200 evaluation boards when they ship later this year; if the sampling results hold, a sub-$5 analog KAN die could displace a $50 edge accelerator module for always-on inference tasks. If you work in semiconductor IP, watch the Twente "in materia" approach, where the silicon's own physics implements the activation function without explicit circuit design; it points toward a future where you characterize whatever nonlinearity your substrate gives you and train the network to exploit it, instead of fighting it with precision ADCs. And if you are benchmarking KANs against MLPs on FLOPs alone, the hardware story says you are measuring the wrong axis entirely: the comparison that matters is energy per correct inference on real silicon, and on that metric, KANs are already winning by nearly two orders of magnitude.