Why are there still GPU shortages if TSMC keeps expanding production?

The constraint isn't transistor fabrication. It's advanced packaging. TSMC's CoWoS packaging capacity can produce approximately 3.65 million AI chip modules in 2026, while industry demand exceeds 4.5-5.0 million modules. Even at 80% annual capacity growth, supply trails demand by 20-27%.

What is CoWoS and why does it matter for AI chips?

CoWoS (Chip on Wafer on Substrate) is TSMC's advanced packaging technology that bonds multiple chiplets and HBM memory stacks onto a silicon interposer. Modern AI GPUs like Nvidia's Blackwell require CoWoS-L packaging, which handles dual-die configurations. Without CoWoS, a manufactured GPU die cannot become a functional chip.

TSMC Makes 3.65 Million AI Chip Modules a Year. The Industry Needs 5 Million. The Bottleneck Isn't Transistors.

Twenty to twenty-seven percent.

That is the gap between how many advanced AI chip modules TSMC can package in 2026 and how many the industry wants to buy. Not transistors. Not wafer starts. Not EUV lithography hours. Packaging. Specifically, a process called CoWoS (Chip on Wafer on Substrate) that bonds GPU chiplets and HBM memory stacks onto a silicon interposer. Without it, a manufactured die is just an expensive piece of silicon that cannot function.

TSMC's CoWoS capacity has been growing at roughly 80% CAGR since 2023, when demand for Nvidia's H100 first overwhelmed supply. By late 2026, TSMC targets 130,000 CoWoS wafer starts per month, up from approximately 60,000 in early 2025. And it is still not enough.

Where the Math Breaks

Building the supply-demand picture requires estimating two numbers: how many CoWoS modules TSMC can produce annually, and how many its customers need.

On the supply side, TSMC's capacity ramp through 2026 looks roughly like this:

Quarter	Est. Monthly Wafer Starts	Quarterly Total
Q1 2026	~70,000	~210,000
Q2 2026	~85,000	~255,000
Q3 2026	~105,000	~315,000
Q4 2026	~130,000	~390,000
Full Year		~1.17 million

Not every wafer produces the same number of modules. CoWoS-S packages (used for single-die GPUs like H200) yield 4-5 modules per 300mm interposer wafer. CoWoS-L packages (used for Blackwell's dual-die GB200 and upcoming Rubin configurations) yield just 2-3 modules. Assuming a 60/40 split favoring CoWoS-L in 2026, the weighted average comes to approximately 3.2 modules per wafer.

That gives us ~3.65 million AI chip modules for the full year.

On the demand side:

Customer	Products	Est. 2026 Module Demand
Nvidia	Blackwell, H200, Rubin	3.0-3.5M
AMD	MI300X, MI400	400-600K
Google	TPU v7/v8	300-500K
Amazon	Trainium v3	200-400K
Microsoft	Maia	100-200K
Others	Startups, inference ASICs	~200K
Total		4.5-5.0M

Supply of 3.65 million versus demand of 4.5-5.0 million: a deficit of 20-27%. And that is after the 80% annual growth in CoWoS capacity.

Nvidia's Allocation Lock

Nvidia has reserved more than 50% of projected CoWoS capacity through at least 2027. Industry estimates put the actual figure closer to 60%. At 3.65 million total modules, that means Nvidia alone absorbs roughly 2.2 million units, leaving the entire rest of the industry to compete for 1.4 million slots.

Google, Amazon, Microsoft, and AMD are all designing custom silicon on TSMC's 3nm process. According to TrendForce, AI now claims 36% of TSMC's 3nm capacity in 2026, up from just 5% in 2025. Each of those chips needs advanced packaging. Every hyperscaler's in-house AI silicon eats into the same CoWoS allocation pool that Nvidia dominates.

Rubin Ultra: Design Shaped by Packaging Physics

Packaging constraints are not merely limiting supply. They are dictating chip architecture. Nvidia's next-generation Rubin Ultra, slated for 2027, was widely rumored to integrate four GPU dies and 16 HBM4E stacks in a single package. Nvidia chose two dies instead.

A four-die configuration would expand the package size to 7.5-8 times the reticle limit, according to TrendForce, destroying both yield and cost economics. TSMC's CoWoS-L process simply cannot produce interposers that large at acceptable rates. So the chip that Jensen Huang will spend a keynote hyping next year was quietly redesigned around a packaging limitation, not a transistor one.

The Reshoring Paradox

Here is the fact that should concern every policymaker who championed the CHIPS and Science Act: wafers fabricated at TSMC's new Arizona fab must be shipped back to Taiwan for advanced packaging. TSMC's CoWoS facilities are concentrated in Hsinchu and planned for expansion in Chiayi and Longtan. None are in the United States.

Congress allocated $52 billion to bring chip manufacturing to American soil. It worked. TSMC Arizona is producing 4nm wafers. But those wafers must cross the Pacific Ocean twice before they become functional AI processors: once as raw silicon to the fab, once as processed wafers back to Taiwan for packaging, and a third time as finished modules to American data centers. Three ocean crossings to make a "domestic" chip.

Intel recognized this gap. Its EMIB (Embedded Multi-die Interconnect Bridge) technology offers the only U.S.-based advanced packaging capability at scale. CEO Dave Zinsner has projected EMIB-related revenue reaching "billions per year," and reports suggest Nvidia is evaluating Intel EMIB for its post-Rubin Feynman architecture. Apple, MediaTek, and Qualcomm are also reportedly in discussions.

Intel's key selling point: unconstrained capacity. While TSMC rations CoWoS slots, Intel has packaging lines sitting underutilized. For customers who cannot secure TSMC allocation, Intel offers a path that stays on American soil.

TSMC's Next Move: Panel-Level Packaging

TSMC is not standing still. On April 13, TrendForce reported that TSMC's CoPoS (Chip-on-Panel-on-Substrate) pilot line has begun receiving tool deliveries, with the full line expected to complete by June 2026. CoPoS replaces the round 12-inch wafer with a square panel format, dramatically improving utilization. As Nvidia's Rubin GPU reaches 5.5x reticle size, a standard wafer can accommodate as few as 4 units. Panels offer a step-change in throughput.

But volume production is not expected until 2028-2029. Warpage at larger substrate sizes remains a major engineering hurdle. For the next two years, CoWoS remains the only game in town for flagship AI chips.

The Strongest Case Against This Thesis

TSMC has a history of beating its own capacity guidance. When the company targeted 60,000 CoWoS wafers per month by early 2025, it arrived slightly ahead of schedule. ASE Technology, the world's largest outsourced assembly and test firm, expects its advanced packaging revenue to double in 2026 as TSMC offloads overflow work. Intel's EMIB could absorb meaningful volume by H2 2026. And if Nvidia's Blackwell ramp is even slightly slower than projected, demand could soften enough to close the gap.

There is real substance here. But even under optimistic assumptions, demand is steepening faster than supply. AI's share of 3nm capacity surging from 5% to 36% in a single year shows acceleration that outpaces any packaging buildout. EMIB serves different market segments (ASICs, mobile SoCs) and does not directly substitute for CoWoS-L on flagship GPU modules. ASE overflow helps at the margin but cannot replicate TSMC's most advanced CoWoS-L processes. And the reshoring gap persists regardless of total capacity.

Limitations

Exact CoWoS allocation by customer is confidential. Nvidia's ">50%" figure comes from industry analyst reports and supply chain sources, not TSMC disclosure. Module-per-wafer estimates vary by package size and generation; our 3.2 weighted average assumes a product mix that could shift. Intel's EMIB revenue projections come from CEO earnings guidance, not confirmed orders. ASE overflow capacity quality and yield data are not publicly available. TSMC's quarterly capacity ramp figures are interpolated from public guidance endpoints, not disclosed monthly data.

What You Can Do

If you are an enterprise buyer planning AI infrastructure: factor 12-18 month lead times for GPU delivery and diversify across Nvidia, AMD, and cloud-provider custom silicon. Do not assume that TSMC's capacity expansion will resolve shortages in 2026.

If you are an investor: watch ASE Technology (3711.TW), which benefits directly from CoWoS overflow. Intel's foundry division is the only pure-play U.S. advanced packaging bet. TSMC's earnings call this week should reveal updated CoWoS capacity guidance.

If you follow AI policy: the CHIPS Act's next reauthorization should explicitly fund domestic advanced packaging facilities, not just wafer fabs. Without U.S.-based CoWoS or equivalent capability, "reshoring" chip manufacturing is an incomplete sentence.

The Bottom Line

For the past three years, GPU shortages have been explained as a demand problem: too many AI companies chasing too few chips. That framing is incomplete. TSMC can fabricate more transistors than ever. What it cannot do, fast enough, is package them. CoWoS is the narrow gate through which every advanced AI chip must pass, and the gate is 20-27% too small. Nvidia's Rubin Ultra was redesigned because of it. Chips made on American soil still fly to Taiwan because of it. Panel-level packaging might fix it, in 2029. Until then, whoever controls packaging allocation controls the AI hardware stack.