Qualcomm Promised $15 Billion in Datacenter Revenue by 2029. Its Current Datacenter Revenue Is Zero.

Zero. That is Qualcomm's datacenter revenue today, rounded to the nearest meaningful digit. Its fiscal 2025 10-K breaks QCT semiconductor revenue into three lines: Handsets ($27.8 billion), Automotive ($4.0 billion), and IoT ($6.6 billion). No datacenter line exists because there is nothing to put on it.

On June 24, 2026, Qualcomm held its Investor Day and told Wall Street it would have $15 billion in datacenter revenue by fiscal 2029. Shares jumped 10% in premarket trading, then kept falling for the rest of the month, shedding 18% from their May high of $251 to land around $182. Investors heard the promise. Then they looked at the calendar.

The Architecture That Has to Work

Qualcomm's datacenter play rests on three bets placed simultaneously. Each depends on the rest. First: a novel chip architecture called High Bandwidth Compute, or HBC. Second: a 250-core server CPU called the Dragonfly C1000. Third: a $3.9 billion all-stock acquisition of Modular, the AI software company founded by Chris Lattner, creator of LLVM, Clang, Swift, and the MLIR compiler infrastructure.

HBC is the most technically ambitious of the three, and the one that requires the most scrutiny. Traditional AI accelerators place compute dies alongside high-bandwidth memory stacks on an expensive silicon interposer, a flat piece of silicon that acts as a highway connecting the two. Nvidia's architecture moves data laterally from HBM stacks to GPU dies. Qualcomm's proposal: skip the interposer entirely, disaggregate the AI accelerator from the main SoC, and bury it directly beneath the DRAM, connecting them vertically through silicon vias, the microscopic copper pillars that punch through layers of a chip.

"Imagine working in the same building that you live in so you only travel up and down," Tony Pialis, Qualcomm's EVP of datacenter, told investors. "The roads are clear."

Qualcomm claims HBC delivers 6x higher bandwidth-per-watt than HBM and 200x the capacity of on-chip SRAM. Its first HBC-based accelerator, the AI250, is due in 2027 and will offer 768 GB of memory and what the company calls 133 TB/s of "effective" memory bandwidth per card. For context, Nvidia's latest inference hardware offers 150 TB/s from dedicated SRAM.

The Bandwidth Number That Doesn't Add Up

Here is where the physics gets interesting. And where the word "effective" earns its quotation marks.

Qualcomm's AI200, shipping later this year, uses LPDDR5X memory. It claims 414 TB/s of "effective" bandwidth across all 56 chips in a full rack, which works out to roughly 7.4 TB/s per chip. Standard LPDDR5X operates at 8,800 megatransfers per second with a 64-bit bus width, yielding approximately 70 GB/s per channel, so achieving 7.4 TB/s of raw, physical bandwidth would require about 106 LPDDR channels on a single chip, aggressive but architecturally plausible.

Now consider the AI250 with HBC: 133 TB/s per card, which Qualcomm says represents an 18x improvement over the AI200's per-card bandwidth. Achieving 133 TB/s of raw LPDDR bandwidth would require roughly 1,900 memory channels on a single accelerator card. That has never been done.

The Register, which covered the announcement in technical detail, put it bluntly: "If that seems too good to be true, that's because it is." When pressed, Qualcomm insisted the figure represents "pure physical bandwidth of the LPDDR interface" but declined to explain how it achieves what would require a bus width that doesn't exist. Peak FLOPS, perhaps the most basic performance metric for any AI accelerator, were "notably missing" from all HBC disclosures, and Qualcomm declined to share specifics when asked directly.

An answer almost certainly lies in compute-in-memory. By performing bandwidth-bound operations like the decode phase of LLM inference directly on the logic die beneath the DRAM, you reduce the amount of data that needs to travel anywhere at all. What Qualcomm calls "effective bandwidth" comes from work that never crosses a bus, measured by a ratio between useful computation and data movement that Qualcomm has not publicly defined. A legitimate engineering approach with real advantages, but calling it "bandwidth" is like calling the time you saved by not commuting "effective highway speed."

The Revenue Ramp Nobody Has Done

Set aside the physics. Consider the business math.

Qualcomm needs to grow datacenter revenue from zero to $15 billion in approximately three fiscal years (FY2027 through FY2029). No precedent exists. For context: AMD, the only company that has successfully challenged Nvidia's datacenter GPU dominance, grew its datacenter GPU revenue from roughly $400 million in 2020 to $6.8 billion in 2024, a four-year ramp that was considered extraordinary at the time. Qualcomm is projecting a trajectory 2.2 times steeper. AMD had a shipping product when it started.

According to MarketsandMarkets, the global AI inference market is projected to reach $255 billion by 2030, growing at a 19.2% CAGR from $106 billion in 2025. Qualcomm's $15 billion target would represent roughly 6% of that market, which sounds modest until you note that Nvidia currently commands more than 80% of AI accelerator revenue and its datacenter segment alone generated $75 billion in a single quarter (Q1 FY2027, reported April 2026), putting its annualized datacenter run rate above $300 billion.

Metric	Qualcomm (FY2025)	Qualcomm (FY2029 Target)	Nvidia (FY2027 Q1 Annualized)
Datacenter revenue	~$0	$15B	~$300B+
Total chip revenue	$38.4B	$58B+ (projected)	~$328B (annualized)
Handset share of chip rev	72%	~33%	N/A
Datacenter customers (named)	0	Meta, Microsoft, Humain	All major hyperscalers
Shipping datacenter product	No	AI200 (2026), AI250 (2027)	Blackwell, Rubin pipeline
Market cap	~$197B		~$4.8T

Named Customers, Unnamed Volumes

Qualcomm's strongest card is not technology. It is the two names attached to it.

Mark Zuckerberg described Meta's commitment as "a multi-generational partnership" and confirmed that Meta will deploy the Dragonfly C1000 server CPU in its infrastructure, with shipments scaling in the second half of 2028. Satya Nadella appeared in a video at the investor event, confirming that Microsoft's Azure cloud division will use Qualcomm's HBC architecture. Saudi-backed AI startup Humain was named as the first AI200 customer, planning to deploy 200 megawatts of Qualcomm rack systems beginning this year. Three customers. None of them small.

Commitments of this caliber matter because they convert an architectural thesis into a deployment roadmap. Meta and Microsoft are not customers who accept slides; they benchmark, they run competitive evaluations, and they demand supply agreements. Whatever skepticism surrounds the "effective bandwidth" number, both companies have evidently seen something in the hardware that justifies a multiyear bet.

But "multi-generational partnership" is a phrase that carefully avoids specifying volume, and Nvidia CEO Jensen Huang recently said that "nearly all major hyperscale cloud providers" are also deploying Nvidia's competing Vera CPU platform, which the company expects to generate nearly $20 billion in CPU revenue in its first year alone. Meta and Microsoft are not choosing Qualcomm instead of Nvidia; they are hedging.

Breaking the CUDA Lock

Qualcomm's $3.9 billion Modular acquisition attempts to solve what has doomed every previous Nvidia challenger: software lock-in. CUDA, Nvidia's programming ecosystem built over 15 years, is the real moat around its datacenter business. Developers write in CUDA, frameworks optimize for CUDA, and switching costs keep everyone locked in place.

Modular's answer is Mojo, a programming language created by Chris Lattner that promises hardware-agnostic AI code. Write once, run on Nvidia GPUs, AMD GPUs, or Qualcomm accelerators. Modular also built Max, a model-serving platform similar to vLLM or SGLang that, in theory, shouldn't require the hand-tuning that alternative hardware typically demands.

Prior CUDA alternatives have not fared well. AMD's ROCm has been available for years and still struggles with compatibility and ecosystem depth. Intel's OneAPI has made little visible dent in developer mindshare. OpenCL, which was supposed to be the vendor-neutral standard a decade ago, remains a niche tool that most AI developers have never touched. Lattner's pedigree is extraordinary and his contributions to compiler infrastructure are foundational, but making developers rewrite their AI stacks is a different problem than building a better compiler, because the friction isn't technical quality. It is inertia, accumulated over fifteen years by millions of developers who have already optimized their workflows around one vendor's tooling and are disinclined to relearn what already works.

Qualcomm's Strongest Card

A study cited during the investor day, by researchers at Google, Microsoft, and several universities, found that AI coding agents consume roughly 1,000 times more inference compute than human programmers performing the same task. A thousandfold. If that ratio holds across agentic AI broadly, inference demand will overwhelm current GPU capacity, and the industry will need architecturally diverse solutions optimized for different phases of the inference pipeline.

Qualcomm's HBC targets the decode phase specifically, where model weights are streamed autoregressively from memory one token at a time and the bottleneck is bandwidth, not compute. In disaggregated inference architectures, GPUs handle the compute-heavy prompt processing (prefill) while specialized hardware handles decode. If this architectural split becomes standard, then Qualcomm doesn't need to beat Nvidia at everything, just at one phase of the pipeline that happens to be the most latency-sensitive and memory-bound, which is precisely the phase where burying compute under DRAM and eliminating the interposer makes the most physical sense.

Economics reinforce this argument: LPDDR is cheaper than HBM, standard packaging is cheaper than advanced CoWoS interposers, and 160 kW per rack is less than what comparable GPU racks consume. If inference cost-per-token is the metric that matters, and if decode is the bottleneck, a chip that trades raw FLOPS for memory proximity could genuinely offer better total cost of ownership, a structural advantage rooted in physics rather than marketing.

Limitations

This analysis relies on publicly available data. Qualcomm has not disclosed: the actual raw bandwidth of its HBC architecture (only "effective" bandwidth, a self-defined metric), peak FLOPS or TOPS for any datacenter accelerator, the definition of its bandwidth multiplier, the computational capabilities of the logic die inside HBC, or any third-party benchmark results. Its $15 billion revenue target is a management projection with no binding commitments attached, and Meta's and Microsoft's announced partnerships do not specify volume, pricing, or guaranteed purchase quantities. AMD's datacenter ramp comparison uses publicly reported revenue figures that include both GPU and CPU sales, which may overstate the GPU-only figure. Nvidia's annualized datacenter revenue is extrapolated from one quarter and may not reflect full-year performance.

What This Means for You

If you are evaluating AI infrastructure purchases for 2027 or beyond, request HBC benchmark data from Qualcomm's datacenter sales team the moment AI250 engineering samples become available. Do not evaluate based on "effective bandwidth" figures alone. Compare decode-phase tokens-per-second-per-watt against Nvidia's Groq LPU and Cerebras WSE-3, the two architectures most directly competing for the same decode-optimized niche. If you are a developer building on CUDA, monitor Mojo's maturity and its actual framework coverage, specifically whether PyTorch and JAX models run without modification, rather than betting on forward-looking compatibility claims. If you are considering Qualcomm stock at its current 17x forward earnings, the question is not whether $15 billion in datacenter revenue is achievable, but whether the path from zero to first significant revenue (the AI200, shipping late 2026) generates enough customer traction to justify the $40 billion non-handset revenue target by FY2029. One number to watch: FY2027 Q1 earnings, when Qualcomm will report the first datacenter revenue figure that isn't zero.

The Bottom Line

Qualcomm is proposing to do something nobody has done: build a datacenter business from nothing to $15 billion in three years, using an architecture that inverts the standard relationship between compute and memory, powered by a software stack that doesn't exist yet, against an incumbent whose annual datacenter revenue exceeds Qualcomm's entire market capitalization. Near-memory compute physics are sound. Decode-optimized inference logic is real. Customers are real. Revenue is not. But the gap between here and there is also real, measured in undisclosed FLOPS, unshipped silicon, and a bandwidth number wrapped in quotation marks.