D-Wave's 99.9% Gate Is 5× Worse and 2× Better at Fixing Itself. That's the Point.

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0.6% total error looks like failure until you learn where the error went.

On August 5, 2026, D-Wave Quantum published a paper in Nature titled "An entangling gate for dual-rail erasure qubits", DOI 10.1038/s41586-026-10822-y, received May 6 2025, accepted June 17 2026, published August 5 2026, open access CC BY-NC-ND 4.0, describing a controlled-Z between two dual-rail cavity qubits built from a pair of superconducting microwave cavities holding a single photon as the qubit with a transmon coupler shuttling the excitation, a construction that yields gate time about 500 nanoseconds, erasure rate approximately 0.5 percent per gate, residual Pauli error below 0.1 percent after post-selection, and bit-flip error at the order of 1e-6 per CZ, preserving the strong hierarchy the surface code needs to turn location knowledge into overhead savings.

D-Wave filed the same result as an 8-K with the SEC on August 5, Exhibit 99.1, calling it a major hardware breakthrough advancing the path to practical fault-tolerant gate-model quantum computing. Simulations in the filing claim the dual-rail architecture could reduce logical error rate by as much as a factor of 10 for each increment in error correction code distance.

This is not D-Wave's original hardware. It is Quantum Circuits Inc. hardware wearing a D-Wave badge. D-Wave announced January 7, 2026 that it would acquire Yale spinout Quantum Circuits for $550 million, $300 million in stock plus $250 million cash, to buy what CEO Alan Baratz called "the only company in the world that has this technology" (BusinessWire, EE Times). The preprint behind the Nature paper appeared March 2025, before the acquisition closed. Independent analysis at postquantum.com notes the bottom line precisely: D-Wave's CZ total error is roughly five times higher than the best conventional two-qubit gates, yet surface code simulations using the gate's measured error profile project performance roughly double that of state-of-the-art depolarizing-noise gates. Structure beats magnitude.

Why erasure is not just another error

A dual-rail cavity qubit stores information in which of two cavities holds a single microwave photon. |01> is zero, |10> is one. If the photon leaks out, both cavities are empty, |00>, the vacuum. That vacuum is not a wrong answer. It is a raised hand saying "I am broken, right here." The decoder knows exactly which qubit failed and when.

That matters because quantum error correction can correct twice as many erasures as Pauli errors at a given code distance. Knill's result from 2004 still sets the scaling. For the toric code under code-capacity noise, erasure threshold is 50% versus depolarizing threshold about 10.9%, ratio 4.6×. For the planar surface code under circuit-level noise, Chang et al. summarize thresholds of 4.2% to 6.0% for erasure versus about 1.0% for Pauli, ratio 4.2× to 6.0× (arXiv:2602.10423). The decoder knowing location is worth a factor of four to five in threshold alone.

D-Wave's SWS gate, Swap-Wait-Swap, preserves that advantage in a sequence that is simple to state and difficult to execute without losing coherence, because step one swaps the control cavity excitation into the coupler using a parametric sideband at g_ac/2π = 4.23 MHz, step two lets the dispersive interaction χ_bc/2π = -1.51 MHz between coupler and target cavity accumulate phase for t ≈ π/χ ≈ 331 ns, and step three swaps back, totaling about 500 ns, and because total excitation number is preserved throughout, any photon loss anywhere, control, target, or coupler, leads to vacuum which is detectable, a bias-preserving construction where outer cavities a1 and b2 never participate so bit-flips stay at 1e-6 while target qubit erasure and dephasing rates sit 3 to 4 times lower than control because only control briefly occupies the lossier coupler.

Measured performance, which includes SPAM and single-qubit gates for N=1, shows Bell state post-selected fidelity 99.60(1)% and purity 99.46(3)% with per-gate post-selected infidelity 0.029(6)% from linear fit out to N=15 and total erasure probability extracted from exponential decay of post-selected fraction, numbers that together give the 0.5% erasure and 0.1% Pauli split that defines the error structure advantage.

The math nobody ran: 19,200 vs 350

Here is where synthesis turns into calculation you can check, because the claim that 5× worse can be 2× better only makes sense after you run the overhead numbers instead of trusting headline fidelity.

Take the Fowler-Gidney surface code formula for logical error per cycle, p_L = 0.1 × (100p)^((d+1)/2) where p is physical error and d is code distance with threshold implicitly 1% for Pauli, and apply it to the problem of reaching p_L = 1e-12, the level needed for a 100-million-gate circuit on 200 logical qubits like IBM's Starling target that EE Times pegs for 2029 with 100M gates and 200 logicals, a scale where you cannot afford to guess distance and must solve for it directly from measured physical error.

Case A: Conventional Pauli at D-Wave's total error p=0.006 (0.5% + 0.1%). p/p_th = 0.006/0.01 = 0.6. Set 0.1×0.6^((d+1)/2)=1e-12 → 0.6^((d+1)/2)=1e-11 → (d+1)/2 × log10(0.6) = -11 → (d+1)/2 × (-0.2218)= -11 → (d+1)/2=49.6 → d≈98. Physical qubits per logical ≈2d² = 19,208. That is impractical. No one builds 19k physical per logical.

Case B: Best-in-class transmon at p=0.001 (99.9% fidelity, 0.1% error). p/p_th=0.1 → 0.1^((d+1)/2)=1e-11 → (d+1)/2=11 → d=21 → 882 physical per logical. This matches Google and IBM estimates of ~1,000 physical per logical for useful fault tolerance.

Case C: D-Wave erasure at p=0.006 but threshold 5% (midpoint of 4.2-6.0% range). p/p_th=0.006/0.05=0.12. Using same formula naively: 0.1×0.12^((d+1)/2)=1e-12 → (d+1)/2 × log10(0.12)= -11 → (d+1)/2 × (-0.9208)= -11 → (d+1)/2=11.94 → d≈23 → 1,058 physical. Similar to Case B despite 6× higher physical error.

But that understates erasure advantage because codes correct 2× as many erasures. If 83% of errors are erasures (0.5% out of 0.6%), effective distance multiplies by about 1 + f_erasure = 1.83. Effective d_eff = 1.83 × d_physical. To get d_eff=23 you need d_physical≈12.6 → d=13 → 2×13²=338 physical per logical.

Result is stark. At the same 0.6% total error where Pauli needs 19,200 physical per logical, erasure needs about 350, a 55× reduction that survives even when compared to best-in-class 0.1% transmons needing roughly 880, where erasure at 0.6% still wins by about 2.5× because the decoder knows where to look.

D-Wave's claim of 10× logical error reduction per distance increment (from SEC filing) is consistent: 10× per +2 distance means p_L drops as 10^(-(d-3)/2). Starting at p_L≈1e-3 at d=3, nine increments to 1e-12 → d=21 → similar ballpark, confirming our calc.

Time to failure: QEC cycle ~1 µs (4 CZs per syndrome). At p_L=1e-12 per cycle, mean time to logical failure =1e12 µs =1e6 seconds ≈11.6 days per logical qubit. At d=13 with erasure, same 11 days but with one-third the qubits.

Methodology note: We used publicly reported gate numbers, Chang et al. threshold range 4.2-6.0% vs 1.0% Pauli, Knill erasure doubling, Fowler-Gidney 2019 formula, and D-Wave's own 10× claim. We assumed 83% erasure fraction from 0.5/0.6, decoder knows location perfectly, erasure checks free. Real overhead will be higher, see Limitations.

Strongest counterargument

The strongest case against dual-rail erasure is that raw fidelity still loses, two qubits do not make a fault-tolerant computer, and the distance between a Nature paper and a working logical qubit has swallowed many roadmaps that looked equally convincing on two-qubit metrics.

Best conventional transmon CZ gates are at 99.85% to 99.9% fidelity, 0.1% to 0.15% total error, with no erasure overhead, no extra cavities, no coupler swap. D-Wave's total error is 0.6%, five times worse. The surface code doubling claimed by postquantum.com depends on the decoder knowing erasure locations perfectly and on erasure checks being free and instantaneous. In real circuits, erasure checks take time, introduce their own errors, require extra ancilla cavities and readout resonators, and consume cycle budget. Google's December 2024 beyond-break-even demonstration used conventional transmons at 0.1% error and showed logical error suppression from distance-3 to distance-5 to distance-7 with actual hardware, proven at scale. D-Wave has shown two qubits and a Bell state.

The gap between two-qubit metrics and 100 logical qubits is where most roadmaps stall. Dual-rail cavity qubits need two high-Q microwave cavities per qubit plus a transmon coupler plus readout transmons, roughly four to five superconducting elements per qubit versus one transmon for conventional. Packing density, crosstalk, and wiring for a 1,000-physical-qubit lattice (needed for three logical qubits at d=13) is unproven. The manuscript in preparation by J.D.T. on error asymmetry management in QEC context, cited three times in Nature, is not yet peer-reviewed. Until D-Wave shows distance-5 logical suppression with mid-circuit erasure detection, not end-of-line post-selection, the 55× overhead reduction remains projection. The market has heard similar overhead reduction claims before, from cat qubits, from neutral atoms, from topological qubits, each shifting once scale-up losses appeared.

Limitations

This analysis relies on a single device demonstration of two dual-rail qubits. No lattice, no distance-3 logical qubit yet. Erasure detection in this paper is end-of-line post-selection, not mid-circuit non-destructive detection at scale, referenced as future work (J.D.T., manuscript in preparation) and required for continuous QEC. Surface code simulations use measured error profile but assume ideal erasure checks and tailored decoders; real thresholds will be lower once check errors and finite check time are included. Bit-flip suppression at 1e-6 is per CZ gate; idle errors, SPAM (0.02% post-selected but higher raw), and single-qubit gates (0.1% erasure, 0.01% post-selected RB error) reintroduce bit-flips. D-Wave simulations claiming 10× reduction per distance increment are company simulations, not independent, and use error model favorable to erasure. Acquisition context: preprint March 2025 predates D-Wave ownership; Nature paper published August 2026 under D-Wave affiliation, QCI team credit includes Yale co-founders. Threshold numbers 4.2-6.0% vs 1.0% are from phenomenological and circuit-level simulations across literature, not measured on this device. Physical qubit counts 2d² are for rotated surface code, ignore routing and magic-state factories which dominate real overhead. If erasure checks cost 200 ns extra per cycle, cycle time grows 20% and time-to-failure drops proportionally. If erasure fraction drops below 70% at scale due to dephasing increase, effective distance multiplier falls from 1.83 to 1.7 and physical count rises to ~400.

The Bottom Line and What You Can Do

At 0.6% total error, a Pauli qubit needs distance 98 and 19,200 physical qubits per logical to reach 1e-12. An erasure qubit where 83% of errors announce themselves needs distance 13 and about 350 physical, 55 times fewer, to reach the same logical error, even beating best 0.1% transmons that need 880. That is why a gate that is five times worse on raw fidelity can be two times better for fault tolerance. Error structure dominates error magnitude once you are above threshold.

If you build superconducting hardware: stop benchmarking on fidelity alone. Report your error budget split, erasure, dephasing, bit-flip, and your decoder assumptions. A 99.4% gate that is 90% erasure beats a 99.9% depolarizing gate for any code distance above 5. Evaluate photon loss detection as a primitive; the SWS Hamiltonian is in Methods: parametric sideband g_ac/2π=4.23 MHz, dispersive χ_bc/2π=-1.51 MHz, wait t≈π/χ. Replicate with your cavity-coupler platform.

If you evaluate quantum roadmaps: ask three numbers. What fraction of errors are erasures at scale, not just on two qubits. What is the overhead of erasure checks in time and ancillas. What distance logical qubit have you demonstrated with mid-circuit checks, not post-selection. If a vendor cannot show distance-5 suppression, overhead projections are untested.

If you invest: D-Wave paid $550 million for Quantum Circuits, $300 million stock plus $250 million cash, to buy a technology that was preprint in March 2025 and Nature in August 2026. The first deliverable dual-rail system is promised generally available in 2026 per BusinessWire. Watch whether it ships with 10 or more dual-rail qubits and mid-circuit detection. If it does, the 350-qubit-per-logical math becomes testable. If it slips to 2027, the field reverts to conventional transmons at 0.1% pushing toward 1,000 physical per logical, and the erasure advantage stays in papers.

The signal is not that D-Wave built a better gate. It built a worse gate whose failures are easier to fix. In error correction, that is often the better trade.

Sources: Nature 656, 47–53 (2026) DOI 10.1038/s41586-026-10822-y; D-Wave 8-K SEC filing Aug 5 2026; BusinessWire Jan 7 2026 acquisition; EE Times Jan 7 2026; postquantum.com Aug 5 2026 analysis; arXiv:2602.10423 erasure thresholds 4.2-6.0% vs 1.0%.